Recently, methods of forming integrated circuit (IC) structures have been developed that enable the formation of a field effect transistor (FET) with an air-gap gate sidewall spacer. With such an air-gap gate sidewall spacer, parasitic capacitance (e.g., the capacitance between the FET gate and the metal plugs on the FET source/drain regions) is reduced as compared to a FET with a conventional gate sidewall spacer. Additionally, methods of forming integrated circuit (IC) structures have been developed that enable the formation of a FET with a gate contact over an active region (CBoA) to allow for area scaling. More specifically, middle of the line (MOL) contacts are contacts that connect field effect transistors (FETs) to the back end of the line (BEOL) metal levels. These MOL contacts include at least one gate contact (CB) and source/drain contacts (CAs). The gate contact extends vertically through the interlayer dielectric (ILD) material from a metal wire or via in the first BEOL metal level (referred to herein as the M0 level) to the gate of the FET. Each source/drain contact extends vertically through the ILD material from a metal wire or via in the first BEOL metal level to a metal plug (TS), which is above and immediately adjacent to a source/drain region of the FET. Conventional techniques for forming these MOL contacts inherently include risks of the following: (a) shorts occurring between the gate contact and a metal plug, particularly, if the gate contact is over an active region or close thereto; and (b) shorts occurring between the source/drain contacts and the gate. However, new techniques have been developed that provide for the formation of these MOL contacts without incurring the above-mentioned risks of shorts. Unfortunately, the techniques used to form a FET with an air-gap gate sidewall spacer are currently incompatible with the techniques used to form a FET with a gate contact over an active region (CBoA).